1. Field of the Invention
The present invention relates to an interface circuit including an open-drain or open-collector transistor.
2. Description of Related Art
FIG. 7 shows an example of a serial interface circuit according to a related art. The serial interface circuit 201 includes a shift register section 210 that receives data in parallel format through an internal bus and outputs the data in serial format to a receiving end, and a baud rate generator 220 that supplies a shift clock to the shift register section 210.
During data transmission, the shift register section 210 receives data in parallel format from a controller (Central Processing Unit or CPU) or the like through an internal bus and outputs the data in serial format through an input/output terminal 216. During data reception, the shift register section 210 receives data in serial format from a receiving end through the input/output terminal 216 and an input buffer 219 and sends the data in parallel format to the CPU. The shift register section 210 includes 8-bit shift registers b0 to b7, for example, and outputs 8-bit serial data each time. The output of the shift register section 210 is connected to the gate of an N-channel transistor 215a of an output section 215 through an inverter 214. The drain of the N-channel transistor 215a is connected to the input/output terminal 216. Thus, the output section 215 has an open-drain configuration.
The input/output terminal 216 is connected to a bus line 217 and further connected to another serial interface circuit (not shown) through the bus line 217. If any of serial interface circuits that are connected to the bus line 217 does not output Low level, the voltage of the bus line 217 is pulled up to a power supply voltage through a pull-up resistor 218.
The baud rate generator 220 receives a basic clock and generates a shift clock at a prescribed frequency (baud rate) The baud rate generator 220 includes a counter 221, a comparator 222 and a ½ frequency divider 223. The baud rate generator 220 counts a basic clock by the counter 221, supplies a clock to the ½ frequency divider 223 at the timing corresponding to a set value of the comparator 222, and outputs a ½ frequency-divided clock as a shift clock. In accordance with the ½ frequency-divided shift clock, shift registers 211 of the shift register section 210 sequentially output data in serial format.
FIG. 8 is a waveform chart of the serial interface circuit. A shift clock having a constant cycle T0 is generated by the baud rate generator, and the data stored in each shift register is output in synchronization with the shift clock. Because the output section 215 has an open-drain configuration, the waveform of data output at a transmitting end is slightly rounded when outputting a High-level signal.
At a receiving end, the output from transmitting end is evaluated with respect to a prescribed threshold level and thereby converted into a pulse signal as shown in the determination result at the receiving end in FIG. 8. However, although the cycle of the shift clock at the transmitting end is constant at T0, the data line is less apt to become High level due to pull-up resistance and therefore the rising edge of the High-level signal is rounded as shown in FIG. 8, which causes the data rate in the receiving-end determination result to appear not to have a constant width. Specifically, the period of Low level before shifting to High level is T2 that is longer than the original cycle T0, and the period of High level after shifting from Low level is T1 that is shorter than the original cycle T0.
A receiver for remote control (which is referred to hereinafter simply as a receiver) with an aim to prevent an error due to a change in pulse width during data exchange with a transmitting end is disclosed in Japanese Unexamined Patent Application Publication No. 10-167009 (Yamamoto). The receiver determines if a bit is “0” or “1” based on a difference in pulse width between High level and Low level. Specifically, it evaluates a received signal with respect to a set value that is set to be narrower or wider than a predetermined pulse width, thereby enabling the bit decision even when a pulse width has changed.
However, the technique taught by Yamamoto needs to add a function for enabling accurate decision even with a changed pulse width to a receiving end, and it is necessary to add the function to each receiving device if there are a large number of receiving devices to receive data from a transmitting end, which causes an increase in system size and costs. Further, because the technique corrects a received signal from the transmitting end by estimating a change, it sometimes fails to provide accurate decision depending on the degree of change. It thus sometimes fails to ensure a desired decision accuracy because it is a system to provide accurate decision based on a change that has already occurred.
Furthermore, because the period of High level at the receiving end is shortened in the open-drain output as described above, it hampers the high-speed transmission. An increase in transmission speed causes failure to transmit a High-level signal to the receiving end, in which case it is difficult to make a correction at the receiving end.